https://mail.coreboot.org/hyperkitty/lis...7P3PFJKBV/
有人想用teensy做一个EHCI调试器。我两个星期前也在想能不能用CH341a和PL2303做。刚刚看了这封邮件,才知道EHCI调试要求480Mbit/s(High Speed),而CH341a和PL2303都只支持12Mbit/s(Full Speed)。STM32F103的USB也是Full Speed,所以也不满足条件。
Debug Port 的说明是在 Enhanced Host Controller Interface Specification for Universal Serial Bus [1] 这个标准里面写的,的确提到了要用 High Speed 设备。
Appendix C. Debug Port
The debug port is an optional implementation feature. This appendix describes the required implementation and behavior of a USB2 Debug Port as part of an EHCI controller. Specific features of this implementation of a debug port are:
• Only works with a high-speed USB debug device
• Implemented for a specific port on the host controller
• Operational anytime the port is not suspended AND the host controller is in D0 power state.
• Capability is interrupted when port is driving USB RESET
[1] https://www.intel.com/content/www/us/en/...r-usb.html
有人想用teensy做一个EHCI调试器。我两个星期前也在想能不能用CH341a和PL2303做。刚刚看了这封邮件,才知道EHCI调试要求480Mbit/s(High Speed),而CH341a和PL2303都只支持12Mbit/s(Full Speed)。STM32F103的USB也是Full Speed,所以也不满足条件。
Debug Port 的说明是在 Enhanced Host Controller Interface Specification for Universal Serial Bus [1] 这个标准里面写的,的确提到了要用 High Speed 设备。
Appendix C. Debug Port
The debug port is an optional implementation feature. This appendix describes the required implementation and behavior of a USB2 Debug Port as part of an EHCI controller. Specific features of this implementation of a debug port are:
• Only works with a high-speed USB debug device
• Implemented for a specific port on the host controller
• Operational anytime the port is not suspended AND the host controller is in D0 power state.
• Capability is interrupted when port is driving USB RESET
[1] https://www.intel.com/content/www/us/en/...r-usb.html